Seiko Epson Develops 32-Bit Single Chip RISC Processor for PDAs

Seiko Epson Develops 32-Bit Single Chip RISC Processor for PDAs


Seiko Epson Corp. announced that it has developed a system LSI, the “S1C38000,” with embedded systems functions for both mobile information appliances and multimedia devices.

Seiko Epson plans to start volume manufacturing and shipping the processors in the third quarter of 2001.

The system LSI uses ARM720T as its microprocessor core, which Seiko Epson developed under a technology license agreement with UK-based ARM Ltd., and integrated all the peripheral circuits into a single chip.

Peripheral circuits of the S1C38000 include: an LCD controller with 112KB display buffer memory, memory interface controller, USB and power management circuit.

It has the interface ports of a 16-pin general purpose input/output, a 21-pin GPIO both for input/output and other functions, and a 13-pin universal output port.

The interface circuits for external memories correspond to ROM, SRAM, flash memory, and SDRAM.

For the package, Seiko Epson adopted the 239-pin ceramic land grid array to realize the smallest assembling area. As a result, the circuit is assembled within around one-fifth of the conventional chip of 208-pin quad flat package.

Though the power consumption of the LSI is around 150mW when it operates at 48MHz, Seiko Epson says it is possible to reduce it to one half or one third of the current power consumption; the low-power-consuming circuit design can sets the clock signal depending on the circuit operation conditions. Notably, for the LCD controller in the processor, it has incorporated RAMs for the display and realizes lower power consumption compared to the conventional processors, the unified memory architecture with external display memories.